D-Matrix Unveils 3D DRAM Breakthrough to Shatter AI Inference Memory Bottlenecks
The new 3DIMC architecture stacks DRAM in three dimensions, reducing latency, dramatically increasing bandwidth, and eliminating the so-called “memory wall.”
AI hardware innovator D-Matrix Corp. has unveiled a transformative advancement in generative AI infrastructure with the integration of 3D DRAM (3DIMC) into its inference compute platform.
The announcement, made during the Hot Chips 2025 conference, marks a bold step toward overcoming one of AI’s biggest bottlenecks: memory bandwidth.
D-Matrix, known for pioneering Digital In-Memory Compute (DIMC), is now fusing memory and compute even more tightly. The new 3DIMC architecture stacks DRAM in three dimensions, reducing latency, dramatically increasing bandwidth, and eliminating the so-called “memory wall.”
“We believe the future of AI inference depends on rethinking not just compute, but memory itself. Today, we are paving the way for a new memory-compute paradigm (3DIMC) that allows our DIMC platform to continue scaling and punch through the memory wall without sacrificing memory capacity and bandwidth,” Sid Sheth, CEO of D-Matrix, said.
As generative AI models grow in size and complexity, traditional HBM-based memory systems have become increasingly power-hungry, costly, and bandwidth-constrained.
D-Matrix’s solution aims to address this at scale—from hyperscale data centers to edge AI deployments—providing an efficient path forward for real-time AI workloads.
